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[VHDL-FPGA-Verilog] RS232

Description: EP2C8Q208_Quartus_V8.0 基于FPGA实现RS232 VHDL代码-EP2C8Q208_Quartus_V8.0 FPGA-based implementation RS232 VHDL code
Platform: | Size: 402432 | Author: zkzkzk | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232 用vhdl语言实现，很有用-RS232 with a vhdl language, very useful
Platform: | Size: 2048 | Author: yuexinqi | Hits:

[VHDL-FPGA-Verilog] FPGA-UART

Description: 该资料是实现VHDL的串口通信(UART)，RS232接口协议，-VHDL implementation of serial communication
Platform: | Size: 2087936 | Author: lp | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 用硬件描述语言VHDL进行串行通信接口电路设计，能通过RS232协议与PC机进行通信。-VHDL hardware description language used for serial communication interface circuit design, through the RS232 protocol to communicate with the PC unit.
Platform: | Size: 785408 | Author: tanzhde | Hits:

[VHDL-FPGA-Verilog] rs232

Description: VHDL 语言如何写串口的源代码，很详细的-VHDL for uart
Platform: | Size: 2048 | Author: 123456 | Hits:

[VHDL-FPGA-Verilog] rs232-demo-for-send-welcome

Description: 这个一个用于fpga上面的串口调试程序，基于vhdl语言编写，可实现welcome字符的现实功能。-Fpga above this one for the serial debugger, based on vhdl language, the reality can be realized characters welcome feature.
Platform: | Size: 3072 | Author: tiger | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: FPGA与计算机基于RS232之间的通信-FPGA and RS232-based communication between the computer
Platform: | Size: 1024 | Author: 王梁 | Hits:

[VHDL-FPGA-Verilog] A-Simplified-VHDL-UART

Description: In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we ll try to build a serial link between 8051 and PC using RS232.
Platform: | Size: 374784 | Author: mezzich | Hits:

[VHDL-FPGA-Verilog] rs232

Description: the vhdl driver:uart communication:rs232(EIA):baud:9600kbps
Platform: | Size: 2048 | Author: guobc | Hits:

[VHDL-FPGA-Verilog] RS232-bus-protocol

Description: 有fpga VHDL原程序 锁脚文件 及下载文件 ，及uart通信协议-Fpga the VHDL program locks the foot of the original files and download files, and uart communication protocol
Platform: | Size: 346112 | Author: 吴信松 | Hits:

[VHDL-FPGA-Verilog] RS232-Simple

Description: A simple UART example for reference in VHDL.
Platform: | Size: 71680 | Author: Cong | Hits:

[VHDL-FPGA-Verilog] rs232

Description: this is vhdl code. purpose of rs-232 connected with altera cyclone2.
Platform: | Size: 94208 | Author: kimjuhyun | Hits:

[VHDL-FPGA-Verilog] RS232

Description: VHDL实现的RS232通信程序，发送和接收都已实现-VHDL realization of RS232 communication procedures, send and receive are realized
Platform: | Size: 200704 | Author: | Hits:

[VHDL-FPGA-Verilog] VHDL-uart

Description: 本程序应用VHDL语言，详细描述了RS232串口协议，包括发送，接收，波特率的产生，模块化编程，对于初学者尤为有宜！-The program in VHDL language, the detailed description of the RS232 serial protocol, including sending, receiving, and baud rate generation, modular programming, especially for beginners should be!
Platform: | Size: 13312 | Author: wangsheng | Hits:

[VHDL-FPGA-Verilog] Rs232-reciever

Description: RS232 reciver vhdl code for RS232 EIA232-RS232 reciver vhdl code for RS232 EIA232
Platform: | Size: 2048 | Author: sgma | Hits:

[VHDL-FPGA-Verilog] RS232uart(VHDL)

Description: rs232串口程序，包括输入和输出，vhdl实现。rs232 serial procedures, including input and output, vhdl implementation.-rs232 serial procedures, including input and output, vhdl implementation.
Platform: | Size: 47104 | Author: houjiajun | Hits:

[VHDL-FPGA-Verilog] puerto-Uart-rs232

Description: UART PORT VHDL USING DE2-115
Platform: | Size: 161792 | Author: crisalex | Hits:

[Other] kehshechenxu

Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。 要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示； 数据格式为1位起始位、8位数据位和一位停止位； 上位计算机发送接收软件可使用“串口调试器“软件； 发送和接收数据时，由两个LED分别指示。 发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button. Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively; The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit; The upper computer sends and receives the software, and the serial debugger can be used; When sending and receiving data, instructions are given by two LED respectively. Play: Auto postback function, receive special characters (custom), change baud rate automatically.)
Platform: | Size: 2948096 | Author: 淡淡的意识 | Hits:

[VHDL-FPGA-Verilog] E8_1_RS232

Description: VHDL编写的RS232串口通讯代码，可以使用。(VHDL prepared by the RS232 serial communication code, you can use.)
Platform: | Size: 762880 | Author: lionsde | Hits:

[VHDL-FPGA-Verilog] rs485

Description: communication rs232 in vhdl with clock divider, counter, buffer, rs232tx, rs232rx.
Platform: | Size: 14336 | Author: le noach | Hits:
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